1. Field of the Invention
The invention relates to semiconductor devices incorporating high dielectric constant insulator materials, and, more particularly, to the use of such materials in microelectronics storage applications.
2. Description of the Related Art
Semiconductor DRAM cells have been developed for storing bits of information in volatile memories. An unrelenting goal in DRAM designs has been to minimize the surface area of the cell and its interconnections in order to achieve very high density memories. However, another important goal in DRAM development has been to maximize the capacitance and storage charge of the storage element. It is important to maintain the magnitude of storage charge despite any reductions in cell sizes to avoid read problems and data integrity problems. Also, an additional emphasis in DRAM development has been to maximize capacitance of the storage element, while still minimizing the overall size of the cell, so that the access time of the storage capacitor, as well as the magnitude of the line signal, is less susceptible to being adversely affected by the parasitic capacitances of the drive lines. Accomplishing both goals of minimizing cell size while increasing storage charge and capacitance has proven challenging from a design standpoint.
As one prior approach to achieve both goals, the cell size has been reduced while increasing capacitance and storage charge by providing a thinner dielectric insulator layer between the capacitor plates. However, punch-through problems have limited the extent to which the conventional dielectric layers can be made thinner. In other prior approaches, further reductions in cell size have been obtained while maintaining the charge holding capacity and capacitance of the storage elements by forming three-dimensional capacitor configurations which construct the capacitor in a location out of the plane of the transistors, such as in so-called stacked, trench, and folded capacitors. These three-dimensional capacitor configurations provide an increase in capacitance without incurring a penalty in area.
As one type of conventional capacitor design, a capacitor can be formed by etching a vertical or nearly vertical deep trench of an aspect ratio of greater than 30:1 into a semiconductor surface of a DRAM integrated circuit and depositing a dielectric material, such as Ta.sub.2 O.sub.5, SiO.sub.2, or SiN.sub.x, on the side walls and bottom of the trench. A trenched DRAM cell structure of this sort is shown in FIG. 1 where trench dielectric material 10 lines the walls of trench 11, where conventionally used dielectric materials 10 in this regard have been Ta.sub.2 O.sub.5, SiO.sub.2, or SiN.sub.x, or a combination of these materials. The trench 11 is then filled with doped polysilicon 12 which forms the second electrode of the capacitor.
In another type of conventional capacitor structure, a stacked capacitor design is shown in FIG. 2, including a substrate 23 having diffusion region 24 formed in its surface and an insulation layer 22 (e.g., silicon dioxide) having a conductive plug 21 (e.g., doped polysilicon or tungsten) formed therein capped with a barrier layer 25 (e.g., WSi.sub.x, TaSiN, TiN, or TiAlN). The bottom electrode 26 (e.g., Pt, Ir, Ru, polysilicon, noble metals, or conductive oxides of noble metals) has its exterior surfaces conformally covered by a dielectric material 27, which, in turn, is covered by top electrode 28, which can be formed of the same materials as described for the bottom electrode 26. As dielectric material 27, SiO.sub.2, SiN.sub.x, or Ta.sub.2 O.sub.5 has been described, or high dielectric materials 27 have also been in the form of various perovskite dielectrics, namely, as BaTiO.sub.3 or SrTiO.sub.3, or other like materials of the perovskite family. The SiO.sub.2 or SiN.sub.x dielectric materials are typically are used in conjunction with polysilicon electrodes, while the perovskite dielectric materials, viz., (Ba,Sr)TiO.sub.3 are used with the other above-mentioned electrode materials.
However, to meet the continuing demands in the industry for even further reductions in the surface area of memory cells, the semiconductor field would be greatly interested in new types of capacitor dielectrics endowed with high capacitance and enhanced charge storage capability as a way of compensating for cell surface area reductions.
A doctoral dissertation by Van S. Nguyen, entitled "Preparation and Photoelectronic Properties of the System Cd.sub.2 Ge.sub.1-x SiO.sub.4 and the Crystallographic and Magnetic Properties of Dispersed Nickel Particles on Spherocarb Supports", Brown University, June 1981, published by UMI Dissertation Services, Bell & Howell Co., Ann Arbor, Mich. 48106, teaches use of an n-type semiconductor material Cd.sub.2 Ge.sub.1-x SiO.sub.4 for preparing a photoanode for photoelectrolysis of water using sunlight. The Nguyen dissertation also teaches Cd.sub.2 GeO.sub.4, Cd.sub.2 SiO.sub.4, Fe.sub.2 GeO.sub.4, and Fe.sub.2 Ge.sub.1-x Si.sub.x O.sub.4 dielectrics which were prepared, or were proposed for future study, for purposes of determining their photo-electronic properties under photoelectrolysis conditions. The Nguyen dissertation does not teach or pertain to microelectronics storage applications such as DRAM device designs.